Copyright(C) 1994,1995,1996,1997 Terumasa KODAKA , Takeshi KONO
■PC-98 bus Plug and Play
Description o Plug and Play is a mechanism for automating board identification, conflict
detection, configuration, and optimizing the allocation of system resources
between systems and other devices without user intervention.
o PC-98 Bus Plug and Play is an extension protocol for implementing Plug and Play
without changing the physical or electrical specifications of the C-bus.
o The I/O ports used in PC-98 bus Plug and Play are provided by each C-bus Plug
and Play compatible expansion board, and are not internal functions. However,
it is possible that various devices within the body provide these I/O ports for
their own Plug and Play purposes.
o The following NEC expansion boards support Plug and Play.
----------------+----------------------------------------
Model name | Product name
----------------+----------------------------------------
PC-9801-99 | Digital video (MPEG) playback board
PC-9801-100 | SCSI-2 interface board
PC-9801-101 | RS-232C expansion interface board
PC-9801-102 | PC card slot expansion board
PC-9801-103 | B4680 interface board EC
PC-9801-104 | B4680 Interface Board ET
PC-9801-110 | Teletext broadcasting receiving board
PC-9801-111 | R8100 interface board
PC-9801-117 | Digital video (MPEG) playback board
PC-9801-118 | Sound board
PC-9821CB-B03 | Digital video (MPEG) playback board
PC-9821CB-B04 | FAX modem board
PC-9821CB2-B03 | TV tuner/video capture board
PC-9821CB2-B04 | FAX modem board
PC-9821CB2-B05 | Digital video (MPEG) playback sub board
PC-9821XA-E01 | PC card slot expansion adapter
PC-9821XE-E01 | PC card slot expansion adapter
AtermIB10･IB11 | LAN compatible ISDN board
----------------+----------------------------------------
Related F000:0000～F000:FFFFh
0000:05B7h
0000:05B8h
I/O 0259h
Name PnP register ADDRESS
Function
[READ] None
[WRITE]
bit 7~0: Register address
Description o Specify the register address to access the Plug and Play registers
o The A5 is reversed from the IBM PC/AT compatible Plug and Play ISA.
Related I/O 0A59h
I/O 0A59h
Name PnP register WRITE_DATA
Function
[READ] None
[WRITE]
bit 7~0: data
---------+-------------------------------------------------
Register | Name
---------+-------------------------------------------------
00h | Set RD_DATA Port
01h | Serial Isolation
02h | Config Control
03h | Wake[CSN]
04h | Resource Data
05h | Status
06h | Card Select Number
07h | Logical Device Numver
---------+-------------------------------------------------
08〜1Fh | Card Level Reserved
---------+-------------------------------------------------
20〜2Fh | Card Level Vendor Defined
---------+-------------------------------------------------
30h | Activate
31h | I/O Range Check
32〜37h | Logical Device Control Reserved
38〜3Fh | Logical Device Control Vendor Defined
---------+-------------------------------------------------
40h | Memory base address bits[23:16] descriptor 0
41h | Memory base address bits[15:08] descriptor 0
42h | Memory Control 0
43h | Memory upper limit address bits[23:16] or
| range length bits[23:16] desctrptor 0
44h | Memory upper limit address bits[15:08] or
| range length bits[15:08] desctrptor 0
45〜47h | Filler
---------+-------------------------------------------------
48〜4Ch | Memory descriptor 1
| * Same as 40~44h
4D〜4Fh | Filler
---------+-------------------------------------------------
50〜54h | Memory descriptor 2
| * Same as 40~44h
55～57h | Filler
---------+-------------------------------------------------
58〜5Ch | Memory descriptor 3
| * Same as 50~54h
5D〜5Fh | Filler
---------+-------------------------------------------------
60h | I/O port base address bits[15:08] descriptor 0
61h | I/O port base address bits[07:00] descriptor 0
62h | I/O port base address bits[15:08] descriptor 1
63h | I/O port base address bits[07:00] descriptor 1
64h | I/O port base address bits[15:08] descriptor 2
65h | I/O port base address bits[07:00] descriptor 2
66h | I/O port base address bits[15:08] descriptor 3
67h | I/O port base address bits[07:00] descriptor 3
68h | I/O port base address bits[15:08] descriptor 4
69h | I/O port base address bits[07:00] descriptor 4
6Ah | I/O port base address bits[15:08] descriptor 5
6Bh | I/O port base address bits[07:00] descriptor 5
6Ch | I/O port base address bits[15:08] descriptor 6
6Dh | I/O port base address bits[07:00] descriptor 6
6Eh | I/O port base address bits[15:08] descriptor 7
6Fh | I/O port base address bits[07:00] descriptor 7
---------+-------------------------------------------------
70h | Interrupt request level select 0
71h | Interrupt request type 0
72h | Interrupt request level select 1
73h | Interrupt request type 1
74h | DMA channel select 0
75h | DMA channel select 1
76h | 32bit Memory base address bits[31:24] descriptor 0
77h | 32bit Memory base address bits[23:16] descriptor 0
78h | 32bit Memory base address bits[15:08] descriptor 0
79h | 32bit Memory base address bits[07:00] descriptor 0
7Ah | 32bit Memory Control 0
7Bh | Memory upper limit address bits[31:24] or
| range length bits[31:24] for descriptor 0
7Ch | Memory upper limit address bits[23:16] or
| range length bits[23:16] for descriptor 0
7Dh | Memory upper limit address bits[15:08] or
| range length bits[15:08] for descriptor 0
7Eh | Memory upper limit address bits[07:00] or
| range length bits[07:00] for descriptor 0
7Fh | Filler
---------+-------------------------------------------------
80〜88h | 32bit Memory descriptor 1
| * Same as 76~7Eh
89〜8Fh | Filler
---------+-------------------------------------------------
90〜98h | 32bit Memory descriptor 2
| * Same as 76~7Eh
99〜9Fh | Filler
---------+-------------------------------------------------
A0～A8h | 32bit Memory descriptor 3
| * Same as 76~7Eh
---------+-------------------------------------------------
A9〜EFh | Logical device configuration reserved
F0〜FEh | Logical device configuration vendor defined
---------+-------------------------------------------------
FFh | Reserved
---------+-------------------------------------------------
* Write the value to the register specified by I/O 0259h
Explanation o Specify the data to be written to the Plug and Play register
Related I/O 0259h
I/O 0003~03FFh
Name PnP register READ_DATA
Function
[READ]
bit 7～0: Plug and Play register read
[WRITE] None
Description o Read the contents of the Plug and Play register specified by I/O 0259h.
o The address of this I/O port is set by Plug and Play register 00h (set RD_DATA port).
The contents to be set are bits 9 to 2 of the address, and the lower two bits of this
I/O port address are always 11b.
o Hardware can be selected from I/O addresses 0003 to 03FFh, but it is normally
recommended to use 0203 to 03FFh.
Related 0000:05B7h
I/O 0259h,0A59h - 00h